spartan-3Eで遊ぶ

まぁ、すでにデザインウェーブでも少しだけ遊んだけど。
評価基板をかったので本格的に遊んでいこうと思う。
とりあえず、動作検証もかねて基本的なところから。
理論より実践！ FPGA開発をスタートしよう（1/3） − ＠IT MONOist
とりあえずこれの流れでやってみた。
ソースは同じだけどUCFを少しいじった。

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "A"  LOC = "L13" | IOSTANDARD = LVTTL | PULLUP; 
NET "B"  LOC = "L14" | IOSTANDARD = LVTTL | PULLUP; 
NET "C"  LOC = "H18" | IOSTANDARD = LVTTL | PULLUP; 
NET "Y[0]"  LOC = "F12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[1]"  LOC = "E12" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[2]"  LOC = "E11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[3]"  LOC = "F11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[4]"  LOC = "C11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[5]"  LOC = "D11" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[6]"  LOC = "E9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 
NET "Y[7]"  LOC = "F9" | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8; 

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

いじったと行っても基本は
Redirect
のユーザーガイド(日本語)に沿ってまねてみただけ。
SLEWとDRIVEがなにを指してるかわからんので後で調べる。
さすがにUSB接続で開発らくだな。
ちなみにverilogの編集エディタはEmeditor。