DCMがうまくつかえない

うーん。結構めんどくさいなぁ。
CLK0の出力は問題ないけど。CLKDVが出力でてないのかなぁ。

普通に使えた。
しかしロックが解除されたときのこと考えてかかないとなぁ。
とりあえずこんな感じでテスト

module led_counter_top(CLK,ENABLE,LED);
    input CLK;
	 input ENABLE;
    output [7:0] LED;
	 
	 
	 wire CLKDV_OUT;
	 wire CLK0;
	 
	 
	// Instantiate the module
	   ledDcm dcm (
		.CLKIN_IN(CLK), 
		.RST_IN(), 
		.CLKDV_OUT(CLKDV_OUT), 
		.CLKIN_IBUFG_OUT(), 
		.CLK0_OUT(CLK0), 
		.LOCKED_OUT(LED[7])
		);
	// Instantiate the module
	led8bitconter led (
		.CNT_CLK(CLKDV_OUT), 
		.ENABLE(ENAB),
		.LED(LED[6:0])
		);
	

endmodule
module led8bitconter(CNT_CLK, ENABLE, LED);
   input CNT_CLK;
   input ENABLE;
   output [6:0] LED;
	 
	parameter SEC = 3125000; //50Mhz /16 *3125000 = 1hz
	
	reg [23:0]tmp_count;
	reg [6:0] tmp_led;
	
	wire sec;
	
	always @(posedge CNT_CLK )
	begin
		if(ENABLE) begin 
			if(sec) 
				tmp_count <= 0;
			else 
				tmp_count <= tmp_count + 1;
		end
	end
	
	assign sec = (tmp_count == (SEC-1))?1'b1:1'b0;
	
	always @(posedge CNT_CLK )
	begin
		if(sec) begin 
			if(tmp_led == 8'h7f) 
				tmp_led <= 0;
			else 
				tmp_led <= tmp_led + 1;
		end
	end
			
	assign LED = tmp_led;
		
			
			

endmodule

ucf

#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "CLK"  LOC = "C9"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 HIGH 50%;
NET "ENABLE"  LOC = "L13"  | IOSTANDARD = LVTTL | PULLUP;
NET "LED[0]"  LOC = "F12"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[1]"  LOC = "E12"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[2]"  LOC = "E11"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[3]"  LOC = "F11"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[4]"  LOC = "C11"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[5]"  LOC = "D11"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[6]"  LOC = "E9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;
NET "LED[7]"  LOC = "F9"  | IOSTANDARD = LVTTL | SLEW = SLOW | DRIVE = 8;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE

とりあえずDMCは使えたけど、FPGAデバッグ手法もそろそろ勉強しておこう。