coreジェネレーターでカウンタ作る
なんか自分で書いた方が早いような気がするけど、やってみた。
とりあえずnew sauceからIPcoreを選択してcounterを探す。
そしたらでてくるので適当に設定したら作ってくれた。とりあえず今回は
4bitのカウンタでLOADピンがhighで値設定が可能な感じのやつ
//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /￥/ / // /___/ ￥ / Vendor: Xilinx // ￥ ￥ ￥/ Version: J.40 // ￥ ￥ Application: netgen // / / Filename: PCNT.v // /___/ /￥ Timestamp: WED 9 JUL 23:14:12 2008 // ￥ ￥ / ￥ // ￥___￥/￥___￥ // // Command : -intstyle ise -w -sim -ofmt verilog C:￥FPGA￥spattan3e￥TD4￥tmp￥_cg￥PCNT.ngc C:￥FPGA￥spattan3e￥TD4￥tmp￥_cg￥PCNT.v // Device : 3s500efg320-4 // Input file : C:/FPGA/spattan3e/TD4/tmp/_cg/PCNT.ngc // Output file : C:/FPGA/spattan3e/TD4/tmp/_cg/PCNT.v // # of Modules : 1 // Design Name : PCNT // Xilinx : C:￥Xilinx92i // // Purpose: // This verilog netlist is a verification model and uses simulation // primitives which may not represent the true implementation of the // device, however the netlist is functionally correct and should not // be modified. This file cannot be synthesized and should only be used // with supported simulation tools. // // Reference: // Development System Reference Guide, Chapter 23 // Synthesis and Simulation Design Guide, Chapter 6 // //////////////////////////////////////////////////////////////////////////////// `timescale 1 ns/1 ps module PCNT ( load, clk, l, q ); input load; input clk; input [3 : 0] l; output [3 : 0] q; // synopsys translate_off wire ￥BU2/N4 ; wire ￥BU2/q_thresh1 ; wire NLW_VCC_P_UNCONNECTED; wire NLW_GND_G_UNCONNECTED; wire [3 : 0] l_2; wire [3 : 0] NlwRenamedSig_OI_q; wire [3 : 0] ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum ; wire [2 : 0] ￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple ; wire [3 : 0] ￥BU2/U0/q_next ; assign l_2[3] = l[3], l_2[2] = l[2], l_2[1] = l[1], l_2[0] = l[0], q[3] = NlwRenamedSig_OI_q[3], q[2] = NlwRenamedSig_OI_q[2], q[1] = NlwRenamedSig_OI_q[1], q[0] = NlwRenamedSig_OI_q[0]; VCC VCC_0 ( .P(NLW_VCC_P_UNCONNECTED) ); GND GND_1 ( .G(NLW_GND_G_UNCONNECTED) ); GND ￥BU2/XST_GND ( .G(￥BU2/N4 ) ); defparam ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<0>1 .INIT = 8'h72; LUT3 ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<0>1 ( .I0(load), .I1(l_2[0]), .I2(NlwRenamedSig_OI_q[0]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0]) ); defparam ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<1>1 .INIT = 8'h72; LUT3 ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<1>1 ( .I0(load), .I1(l_2[1]), .I2(NlwRenamedSig_OI_q[1]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [1]) ); defparam ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<2>1 .INIT = 8'h72; LUT3 ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<2>1 ( .I0(load), .I1(l_2[2]), .I2(NlwRenamedSig_OI_q[2]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [2]) ); defparam ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<3>1 .INIT = 8'h72; LUT3 ￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum<3>1 ( .I0(load), .I1(l_2[3]), .I2(NlwRenamedSig_OI_q[3]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [3]) ); MUXCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrymux0 ( .CI(￥BU2/q_thresh1 ), .DI(load), .S(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [0]) ); XORCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxor0 ( .CI(￥BU2/q_thresh1 ), .LI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [0]), .O(￥BU2/U0/q_next [0]) ); XORCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carryxortop ( .CI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [2]), .LI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [3]), .O(￥BU2/U0/q_next [3]) ); MUXCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carrymux ( .CI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [0]), .DI(load), .S(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [1]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [1]) ); XORCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[1].carryxor ( .CI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [0]), .LI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [1]), .O(￥BU2/U0/q_next [1]) ); MUXCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[2].carrymux ( .CI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [1]), .DI(load), .S(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [2]), .O(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [2]) ); XORCY ￥BU2/U0/the_addsub/no_pipelining.the_addsub/i_simple_model.carrychaingen[2].carryxor ( .CI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/carry_simple [1]), .LI(￥BU2/U0/the_addsub/no_pipelining.the_addsub/halfsum [2]), .O(￥BU2/U0/q_next [2]) ); defparam ￥BU2/U0/q_i_0 .INIT = 1'b0; FDE ￥BU2/U0/q_i_0 ( .C(clk), .CE(￥BU2/q_thresh1 ), .D(￥BU2/U0/q_next [0]), .Q(NlwRenamedSig_OI_q[0]) ); defparam ￥BU2/U0/q_i_1 .INIT = 1'b0; FDE ￥BU2/U0/q_i_1 ( .C(clk), .CE(￥BU2/q_thresh1 ), .D(￥BU2/U0/q_next [1]), .Q(NlwRenamedSig_OI_q[1]) ); defparam ￥BU2/U0/q_i_2 .INIT = 1'b0; FDE ￥BU2/U0/q_i_2 ( .C(clk), .CE(￥BU2/q_thresh1 ), .D(￥BU2/U0/q_next [2]), .Q(NlwRenamedSig_OI_q[2]) ); defparam ￥BU2/U0/q_i_3 .INIT = 1'b0; FDE ￥BU2/U0/q_i_3 ( .C(clk), .CE(￥BU2/q_thresh1 ), .D(￥BU2/U0/q_next [3]), .Q(NlwRenamedSig_OI_q[3]) ); VCC ￥BU2/XST_VCC ( .P(￥BU2/q_thresh1 ) ); // synopsys translate_on endmodule // synopsys translate_off `timescale 1 ps / 1 ps module glbl (); parameter ROC_WIDTH = 100000; parameter TOC_WIDTH = 0; wire GSR; wire GTS; wire PRLD; reg GSR_int; reg GTS_int; reg PRLD_int; //-------- JTAG Globals -------------- wire JTAG_TDO_GLBL; wire JTAG_TCK_GLBL; wire JTAG_TDI_GLBL; wire JTAG_TMS_GLBL; wire JTAG_TRST_GLBL; reg JTAG_CAPTURE_GLBL; reg JTAG_RESET_GLBL; reg JTAG_SHIFT_GLBL; reg JTAG_UPDATE_GLBL; reg JTAG_SEL1_GLBL = 0; reg JTAG_SEL2_GLBL = 0 ; reg JTAG_SEL3_GLBL = 0; reg JTAG_SEL4_GLBL = 0; reg JTAG_USER_TDO1_GLBL = 1'bz; reg JTAG_USER_TDO2_GLBL = 1'bz; reg JTAG_USER_TDO3_GLBL = 1'bz; reg JTAG_USER_TDO4_GLBL = 1'bz; assign (weak1, weak0) GSR = GSR_int; assign (weak1, weak0) GTS = GTS_int; assign (weak1, weak0) PRLD = PRLD_int; initial begin GSR_int = 1'b1; PRLD_int = 1'b1; #(ROC_WIDTH) GSR_int = 1'b0; PRLD_int = 1'b0; end initial begin GTS_int = 1'b1; #(TOC_WIDTH) GTS_int = 1'b0; end endmodule endmodule
なんか無駄に長いな。
