std_logic と std_logic_vectorの代入

std_logicからstd_logic_vectorへ

signal a : std_logic;
signal b : std_logic_vector(0 downto 0);
begin
b(0) <= a;

std_logic_vectorからstd_logicへ

signal a : std_logic;
signal b : std_logic_vector(0 downto 0);
begin
a <= b(0);

xilinxのilaとかvioで必要になるのでメモ